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Microcode Subroutine Nesting with Conditional Returns

IP.com Disclosure Number: IPCOM000089651D
Original Publication Date: 1977-Dec-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 4 page(s) / 47K

Publishing Venue

IBM

Related People

Grice, LE: AUTHOR [+3]

Abstract

Microcode subroutine nesting apparatus is described which has provision for conditional returns and which obviates the need for an incrementing read-only storage address register (ROSAR) or incrementing read-only storage (ROS) link registers.

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Microcode Subroutine Nesting with Conditional Returns

Microcode subroutine nesting apparatus is described which has provision for conditional returns and which obviates the need for an incrementing read-only storage address register (ROSAR) or incrementing read-only storage (ROS) link registers.

The apparatus is described with respect to a processor, such as an individual processor used in the IBM Series/1 system. A processor of this nature is controlled by a ROS, which takes only as many microprogram cycles as is necessary to execute each machine level instruction. During each microcycle the contents of one "source" register are gated to a bidirectional processor bus (not shown), and one or more "destination" registers are loaded from this bus. The Series/1 processor uses a 1536 X 32 ROS. Each 32 bit ROS word includes 22 bits to control the data flow and 10 bits, ROSAR bits 1 to 10 (Fig. 4) which are used to form a next address (NA) field for accessing the next microword to be executed. The high-order bit illustrated in Fig. 4 is controlled by hardware and microcode via latch 1, line 2 and AND gate 3 (Fig. 1). The high-order bits 0 and 1 determine which of the four areas of ROS are being addressed to select a next microword for execution.

For each level of subroutine nesting, there is a ROS LR comprised of polarity hold (PH) stages. These are designated ROS LR1 and ROS LR2 in Fig. 1, and each has a corresponding associated latch SR1 and SR2. These latches are coupled to ROS LR1 and ROS LR2 by AND gates 4 and 5, respectively. When a branch is made, SR1 or SR2 cause the NA value in ROSAR to be updated by exclusive OR circuit 6 and inverter 7 and stored in ROS LR1 and ROS LR2.

Initiation. At the beginning of the execution of each machine level instruction, a force is made via ROSAR to one of a plurality of instruction execution entry locations in ROS. During the subsequent microword execution of the machine level instruction, the latch 1 and either the NA field from the ROS data register (ROSDR) or the contents of ROS LR1 and ROS LR2 specify the next ROS word to be executed.

Termination. Execution of the machine level instruction is terminated by decoding a unique NA value as the last microword in the subroutine. When this value is decoded, the SR1 and SR2 latches are reset and the execution of a new instruction is initiated via another initial entry. Class interrupts, such as machine check, also terminate the execution of a machine level instruction, reset SR1 and SR2, and force a branch to the initial entry location of the class interrupt microcode.

ROS Link Registers and Timings. The clock times A and C are shown in Fig.
2. Every Time C clocks the ROSAR. Every Time A clocks the ROSDR. Every Time A, except when the Subroutine 1 (SR1) latch is on, clocks ROSAR bits 1-8 into ROS link register 1 (ROS LR1) bits 1-8, while ROSAR bits 9-10 go through a two-bit incrementer into ROS LR1 bits 9-10 (Fig. 3). The effect of this is to set the...