Browse Prior Art Database

Latched ALU Controls for Overlapped Data Flow Operations and Control

IP.com Disclosure Number: IPCOM000089654D
Original Publication Date: 1977-Dec-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 30K

Publishing Venue

IBM

Related People

Tutt, WE: AUTHOR

Abstract

This feature enables repetitive data operations to continue while executing other control instructions. It involves arithmetic and logic unit (ALU) controls for iterative processing. Performance is thereby increased, and the total number of micro-word control instructions is decreased. It has particular utility in systems such as the IBM Series/1 computers, and is used during storage address modifications.

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Latched ALU Controls for Overlapped Data Flow Operations and Control

This feature enables repetitive data operations to continue while executing other control instructions. It involves arithmetic and logic unit (ALU) controls for iterative processing. Performance is thereby increased, and the total number of micro-word control instructions is decreased. It has particular utility in systems such as the IBM Series/1 computers, and is used during storage address modifications.

In the drawing, an ALU 1 has associated A, B and B* registers, designated 3, 4 and 5, respectively. Using latched ALU controls signals on line 6, ALU input registers A and B, and controls to load the ALU result into register B at the end of each machine cycle, data A and B are repetitively combined according to the latched ALU controls. If, for example, the controls specify B+A, the operation will continue until explicitly stopped or until one of the registers is altered by an explicit instruction. A sum of B+A+A+A+A+.. is formed.

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