Browse Prior Art Database

Stop Clock to Save Read Only Storage

IP.com Disclosure Number: IPCOM000089655D
Original Publication Date: 1977-Dec-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 50K

Publishing Venue

IBM

Related People

Birney, RE: AUTHOR [+2]

Abstract

Some central processing units (CPUs), such as the IBM Series/1 Model 5 (4955), include read-only storage (ROS), and each instruction takes only as many microcycles as necessary. This CPU, for example, uses a 1536 X 32 ROS, which is a relatively small ROS for the complexity of its instruction set. The basic machine clock of 220 nanoseconds is divided into four subpulses, called A, B, C and D, of 55 nanoseconds each.

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Stop Clock to Save Read Only Storage

Some central processing units (CPUs), such as the IBM Series/1 Model 5 (4955), include read-only storage (ROS), and each instruction takes only as many microcycles as necessary. This CPU, for example, uses a 1536 X 32 ROS, which is a relatively small ROS for the complexity of its instruction set. The basic machine clock of 220 nanoseconds is divided into four subpulses, called A, B, C and D, of 55 nanoseconds each.

The feature described here saves approximately 3 to 4% of the ROS words by stopping the clock instead of using blank ROS words for No Operations (NOPs). The NOPs are required sometimes to fill out storage cycles (there being 3 microcycles in one storage cycle) and sometimes for delaying after a condition is set before doing a conditional ROS branch on that condition (due to the 3 microcycle overlap scheme used in the CPU).

The way this scheme is implemented in the CPU is to have one microcontrol for one NOP activated by control line 1 and another microcontrol for two NOPs activated by control line 2. This scheme could be expanded to as many NOPs as required; however, typically, the processor has no need for more than two NOPs.

The basic logic diagram is shown in Fig. 1. The A, B, C and D clock 9 times are indicated in Fig. 2. The terminology used is as follows: & - AND circuit L - Latch CLK - Clock N - Inverter CTL - Control NOP - No operation D:CD - Decode Or - OR circuit DLY - Delay PH - Polarity Hold DOT - Wired...