Browse Prior Art Database

Microcode Storage Controls

IP.com Disclosure Number: IPCOM000089657D
Original Publication Date: 1977-Dec-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 3 page(s) / 42K

Publishing Venue

IBM

Related People

Grice, LE: AUTHOR [+2]

Abstract

The IBM Series/1 Model 5 (4955) central processing unit (CPU) has a 1536 X 32 read-only storage (ROS). The 32 bits are defined in the article found on page 2566 of this publication. The storage controls are specified by ROS bits 13-15 unless the destination field specifies an emit.

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Microcode Storage Controls

The IBM Series/1 Model 5 (4955) central processing unit (CPU) has a 1536 X 32 read-only storage (ROS). The 32 bits are defined in the article found on page 2566 of this publication. The storage controls are specified by ROS bits 13- 15 unless the destination field specifies an emit.

A substantial savings of ROS words is achieved here by allowing common subroutines to do different things. The Storage Control Decodes that are used are: 0 - No storage cycle 1 - SR - Change the next LW or SW to Load or Store Segmentation Register, if translator is installed. If translator is not installed, set invalid function program check. 2 - BR - Block the next LW or SW 3 - SBY - Change the next LW or SW into a byte request instead of a word request. Also, change the next clock result indicator control into a clock byte result indicator. 4 - LIW - Load instruction word into SDR. 5 - BTR - Block this request (used only in the microcycle immediately following an LIW, LW, or SW). 6 - LW - Load data word (two bytes) into SDR. 7 - SW - Store data word from SDR into storage. Other abbreviations used are: A - AND Circuit OR - OR Circuit BLK - Block PH - Polarity Hold CHK - Check PROC - Processor, CPU CTL - Control REQ - Request D:CD - Decode ROS - Read-Only Storage DR - Data Register SDR - Storage Data Register LT - Latch STG - Storage

The storage control words from ROS 1 are transferred to the ROS Data Register 2, and decoded by block 3 (Fig. 1).

Fig. 4 shows the simplified storage control logic involved. Three of the ROS bits from Fig. 1 are decoded to form various types of storage requests and directed as inputs...