Browse Prior Art Database

Specify Microcode Emit by Destination Field

IP.com Disclosure Number: IPCOM000089658D
Original Publication Date: 1977-Dec-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

Grice, LE: AUTHOR [+2]

Abstract

The IBM Series/1 Model 5 (4955) central processing unit (CPU) has a 1536 X 32 read-only storage (ROS). The 32 bits are laid out as shown in Fig. 1.

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Specify Microcode Emit by Destination Field

The IBM Series/1 Model 5 (4955) central processing unit (CPU) has a 1536 X 32 read-only storage (ROS). The 32 bits are laid out as shown in Fig. 1.

Fig. 2 illustrates ROS 1, ROS data register 2, emitter registers 3 and 4, destination decode blocks 5, 6a-6n and processor bus 8. Fig. 3 shows data transfer timing.

By using some decodes in the Destination field, a unique emit bit was saved. By using 8-bit emits the Control field can still be used, thus saving ROS words. The following abbreviations are found in the drawings: ALU - Arithmetic and Logic Unit EMIT - Emitter CLK - Clock PROC - Processor COND - Conditional REG - Register CTRL - Control ROS - Read- Only DEST. A - Destination A Storage Dest. n - Destination n STG - Storage

The 95 control decodes control various things in the CPU. The 32 conditional ROS branches allow the microcode to branch different places depending on machine conditions. The Source field specifies what source is to be gated onto the processor bus 8. The Destination field specifies one or more destinations to be loaded from the processor bus. The Next ROS Address field specifies the next ROS word to be executed.

Four of the destination decodes from block 5 specify the destination through blocks 6a-6n and also activate emitter registers 3 and 4 to emit ROS bits 0-15 to the processor bus 8 as a source. Twelve destination decodes specify to emitter register 4 to emit ROS bits 8-15 to the processor bu...