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Teleprocessing Bit Rate Control Circuit

IP.com Disclosure Number: IPCOM000089661D
Original Publication Date: 1977-Dec-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 58K

Publishing Venue

IBM

Related People

Thornley, JS: AUTHOR

Abstract

The feature described offers a number of advantages in connection with systems, such as the IBM Series/1 computers. It eliminates the need for hardware jumpers to control the bit rate of communication attachments. It allows communication attachments to operate at many different bit rates. It allows modulation of the width of each individual bit of the serial data. This technique can be used as a form of cryptography.

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Teleprocessing Bit Rate Control Circuit

The feature described offers a number of advantages in connection with systems, such as the IBM Series/1 computers. It eliminates the need for hardware jumpers to control the bit rate of communication attachments. It allows communication attachments to operate at many different bit rates. It allows modulation of the width of each individual bit of the serial data. This technique can be used as a form of cryptography.

The circuit (Fig. 1) includes a Register A (Reg A) for holding a binary value. The contents of Register A can be changed by activating the load line 1, with the appropriate value to be applied to the inputs of Register A. This lends itself to control by a computer. The value contained in Register A is transferred into a Count-down Register (CDR) where the value is decremented to zero. Upon decrementing to zero, the value is again transferred from Register A to the Count-down Register. Thus the frequency at which the Count-down Register is decremented to zero can be controlled by the binary value contained in Register
A.

The loading of the Count-down Register from Register A is controlled by clock lines 2, 3 and 4, which are derived from the decode of a two-stage Binary Counter 6. Counter 6 also drives the Count-down Register. The clocks are sequential, as indicated in the timing chart (Fig. 2), and they are gated by the Count-down Register decrementing to zero. At this time clock 2 resets the Count-down Registe...