Browse Prior Art Database

Intermediate Status

IP.com Disclosure Number: IPCOM000089666D
Original Publication Date: 1977-Dec-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 24K

Publishing Venue

IBM

Related People

Devore, EW: AUTHOR [+4]

Abstract

Some digital data recorders transfer previously recorded signals in long bursts of a succession of independent data records, each independent data record having its own error detection and correction check bytes. At an intermediate point in the transfer path, check bytes are stripped from the data stream, and status signals relating to the readback operation are substituted for the check bytes for enhancing error recovery procedures in the event of an equipment error condition.

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Intermediate Status

Some digital data recorders transfer previously recorded signals in long bursts of a succession of independent data records, each independent data record having its own error detection and correction check bytes. At an intermediate point in the transfer path, check bytes are stripped from the data stream, and status signals relating to the readback operation are substituted for the check bytes for enhancing error recovery procedures in the event of an equipment error condition.

A memory device, such as a magnetic tape unit, supplies data signals over line A to a memory controller. Such data signals include a plurality of records R1, R2, R3... with respective appended check bytes C1, C2, C3... The memory controller computes error syndromes based upon a comparison of the data signals and the respective check signals; that is, R1 and C1 are combined to provide error syndromes, as is well known. Similarly, the other independent records R2, R3 and so forth are compared with their check bytes. As the data is transferred by the memory controller to a utilization device, such as a host CPU, the check bytes are stripped from the data stream, and the data stream changes, as shown at B, wherein status signals S1, 52... are substituted for the check bytes. Such status bytes indicate the operational status of the memory device and the memory controller, as well as flag errors that are detected in the various records. Note that the last two sets of bytes pr...