Browse Prior Art Database

Step Oxide Ion Implanted Memory

IP.com Disclosure Number: IPCOM000089669D
Original Publication Date: 1977-Dec-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 36K

Publishing Venue

IBM

Related People

Lee, HS: AUTHOR

Abstract

This semiconductor memory produced in a unipolar technology has cells of the type described in U. S. Patent 4,040,017, but does not require applying a negative bias voltage on a word line 10, shown in the figure, to prevent charge spill over from one cell to another cell when the word line 10 is unselected and during the disturb condition. Surface tailoring, as indicated by regions P+, and a relatively thick oxide 12 between the word line 10 and regions P+ provide a potential barrier when the word line voltage is turned off.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 62% of the total text.

Page 1 of 2

Step Oxide Ion Implanted Memory

This semiconductor memory produced in a unipolar technology has cells of the type described in U. S. Patent 4,040,017, but does not require applying a negative bias voltage on a word line 10, shown in the figure, to prevent charge spill over from one cell to another cell when the word line 10 is unselected and during the disturb condition. Surface tailoring, as indicated by regions P+, and a relatively thick oxide 12 between the word line 10 and regions P+ provide a potential barrier when the word line voltage is turned off.

The process for making this memory includes forming channel-defining areas parallel to the word line 10 by employing well-known recessed oxide techniques with a boron implant or by growing a thick oxide of about 7,000 Angstroms.

The cells 14, 16 and 18, as inversion capacitors, are made by growing an approximately 500 Angstroms-thick layer 20 of silicon dioxide over the surface of a P-type silicon substrate 22, followed by a layer of doped polysilicon which is oxidized and suitably etched to form diffused N+ charge injection regions in the substrate 22. The polysilicon layer is then etched to form bit/sense lines 24, 26 and 28. The surface of the substrate 22 between adjacent bit/sense lines 24, 26 and 28 is tailored by implanting ion, e.g., boron, through the silicon dioxide layer 20 to form the P+ regions. A typical dosage for forming these P+ regions is 2 x 10/12/ e/cm/2/ at 50 KeV.

The silicon dioxide betwe...