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Browse Prior Art Database

Ultra Thin Layer Transistors

IP.com Disclosure Number: IPCOM000089671D
Original Publication Date: 1977-Dec-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 51K

Publishing Venue

IBM

Related People

Geipel, HJ: AUTHOR [+3]

Abstract

An extremely shallow emitter and a narrow base width are provided in a transistor by recoil implantation of ions through a doped polysilicon layer.

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Ultra Thin Layer Transistors

An extremely shallow emitter and a narrow base width are provided in a transistor by recoil implantation of ions through a doped polysilicon layer.

The process for making the transistor includes forming a silicon dioxide layer 10 on an N-type silicon substrate 12 and providing an opening 13, as indicated in Fig. 1, therein for implanting, e.g., with boron, the base 14 of the transistor, with the substrate 12 acting as the transistor collector. After the boron is implanted into the collector or substrate 12, the surface of the base 14 at the opening 13 is reoxidized. By properly controlling the implant energy and taking into consideration subsequent high temperature treatments, a preselected base depth d(2) can be realized with repeatable accuracy.

To prepare for the emitter formation, the oxide layer 10 is again selectively removed to provide an opening 15 within the surface area of the base 14, as indicated in Fig. 2. Over the oxide layer 10 and the surface of the base 14 within the opening 15, there is deposited a layer of N-doped polysilicon 16. The dopant, e.g., arsenic, may be implanted or in situ, and the layer 16 may be 2000 Angstroms thick. The polysilicon layer 16 is now removed except for the portion 18 deposited in the region of the opening 15, as shown in Fig. 3. If desired, the exposed surface of the oxide layer 10 is covered with a photoresist (not shown) without depositing the photoresist on the polysilicon portion 18,...