Browse Prior Art Database

Self Aligned Gate Contact Memory Process

IP.com Disclosure Number: IPCOM000089672D
Original Publication Date: 1977-Dec-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 47K

Publishing Venue

IBM

Related People

Geipel, HJ: AUTHOR [+3]

Abstract

A process for making a very small, one-device memory cell utilizes a polysilicon plate 7 which overlaps a polysilicon gate 4, and provides a self-aligned gate contact by using a dip etch technique. The cell employs inversion storage.

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Self Aligned Gate Contact Memory Process

A process for making a very small, one-device memory cell utilizes a polysilicon plate 7 which overlaps a polysilicon gate 4, and provides a self- aligned gate contact by using a dip etch technique. The cell employs inversion storage.

As indicated in Fig. 1, recessed oxide isolation regions 2 are formed in a silicon substrate 11 by utilizing a suitable mask which may include a silicon dioxide layer 3 and a silicon nitride layer 1. After the oxide regions 2 are formed and the mask 3,1 is stripped from substrate 11, a gate oxide 3' is grown, over which a first doped layer of polysilicon 4 is deposited followed by a layer of silicon nitride 5. A thin layer of about 100 angstroms of silicon dioxide (not shown) may be grown for adhesion purposes over the polysilicon layer 4 before depositing the silicon nitride layer 5. By employing suitable masking techniques, the oxide layer 3', polysilicon layer 4 and the nitride layer 5 are etched to form the polysilicon gate 4, as illustrated in Fig. 2, and an oxide layer 6 is grown to form the dielectric for the storage node of the cell.

A second doped layer of polysilicon is deposited over the oxide layer 6 and the nitride layer 5 and etched to form the plate 7 of the cell's storage node. A diffusion region 9, seen in Fig. 3, which can be used as the bit/sense line of the memory, is then provided by any known process. Oxide layers 10 and 6' are now grown over the polysilicon plate 7 and...