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High Gain Sense Amplifier

IP.com Disclosure Number: IPCOM000089679D
Original Publication Date: 1977-Dec-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 3 page(s) / 37K

Publishing Venue

IBM

Related People

Chakravarti, SN: AUTHOR [+3]

Abstract

This sense amplifier provides high gain without the use of special stabilizing circuitry. The amplifier is related to and is a simplification of the sense amplifier illustrated and described in IBM Technical Disclosure Bulletin 19, 713 (July 1976).

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High Gain Sense Amplifier

This sense amplifier provides high gain without the use of special stabilizing circuitry. The amplifier is related to and is a simplification of the sense amplifier illustrated and described in IBM Technical Disclosure Bulletin 19, 713 (July 1976).

The sense amplifier, shown in Fig. 1 in the single-ended configuration, utilizes the timing diagram indicated in Fig. 2. The amplifier includes four similar inverter stages cascaded together. The four stages include field-effect transistors T1 and T2, T3 and T4, T5 and T6, and T7 and T8. Bit/sense line BSL1 connected to the gate electrode of transistor T1 is precharged by turning on the load devices T2, T4, T6 and T8 with the Phi 1 pulse going up and also closing the negative feedback loop through switch T10 with Phi 2 pulsed high. The bit/sense line BSL1 is adjusted to an intermediate level of voltage between VH and ground, plus or minus a differential voltage which is proportional to the direct current offset voltage of the amplifier. Such offset voltage is caused by variations in threshold voltage Vt, amplification factor gm, etc., of the transistors, and a function of power supply voltage and temperature.

If the feedback switch T10 is now opened, a compensated offset signal is stored on the bit/sense line, the compensation factor being equal to 1/(1 + A Gamma), where A Gamma is the open loop voltage gain of the three-stage amplifier. The amplifier is now ready for amplification of any signal appearing on the bit/sense line. An input signal is produced by turning on an array device T9 as EVW goes high, thus transferring charge between the storage node capacitance CSN and the bit/sense line BSL1. The bit/sense line BSL1 is either charged or discharged by a charge difference which depends on whether a 1 or a 0 bit of information...