Browse Prior Art Database

MC Cermet SiO(2) Passivation Process

IP.com Disclosure Number: IPCOM000089691D
Original Publication Date: 1977-Dec-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Hoffman, HS: AUTHOR

Abstract

The present process is adapted for the manufacture of low tolerance or precision resistors which require a high degree of stability. The process involves selectively etching the quartz over the resistor and then metallizing. The process and resulting cermet resistor is shown and described in the figures.

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MC Cermet SiO(2) Passivation Process

The present process is adapted for the manufacture of low tolerance or precision resistors which require a high degree of stability. The process involves selectively etching the quartz over the resistor and then metallizing. The process and resulting cermet resistor is shown and described in the figures.

An SiO(2) overlay is applied over the metallized ceramic (MC) cermet resistor, and is compatible with the MC process in the following ways: (1) Accounts for Cr/Cu/Cr versus Cu/Cr electrodes, with the additional Cr layer providing needed adhesion between the cermet and Cu. (2) Allows for proper electrical contact of Cr/Cu/Cr electrodes to the cermet resistor. (3) Protects the cermet resistor from MC chemicals.

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