Browse Prior Art Database

Thermally Enhanced Package for Semiconductor Devices

IP.com Disclosure Number: IPCOM000089696D
Original Publication Date: 1977-Dec-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 37K

Publishing Venue

IBM

Related People

Foster, RA: AUTHOR [+2]

Abstract

It is highly desirable to be able to improve the allowable power dissipation in metallized ceramic packages. This requires that an improved heat transfer path from the chip device to the ambient environment be provided.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 77% of the total text.

Page 1 of 2

Thermally Enhanced Package for Semiconductor Devices

It is highly desirable to be able to improve the allowable power dissipation in metallized ceramic packages. This requires that an improved heat transfer path from the chip device to the ambient environment be provided.

One way for accomplishing this, using the so-called flip chip attachment of the circuit chips to the substrate, is shown in Fig. 1. The package includes a ceramic carrier substrate 11, with a semiconductor device 13 mounted on the surface of the substrate via, for example, solder balls. A cover 15 surrounds the ceramic substrate and has an appropriate seal 17 around its periphery and around the I/O pins 19. The metallized ceramic substrate has a normal thickness of, for example, 60 mils, but in the area of the chip, the ceramic substrate has a reduced thickness of, for example, 10 mils. Into this reduced thickness pocket, a thermal interposer 21 is bonded, which may be a molybdenum stud suitably brazed to the ceramic substrate. Heat sink pins 23 for thermal conduction are bonded to the interposer 21 or may be an integral part of it. These pins provide a thermally conductive path to the next packaging level carrier 25 and to the ambient. Further, a suitable heat sink may be attached to the pins 23 after it passes through the carrier 25.

An alternative configuration is shown in Fig. 2 when using back-bonded chips. With this configuration, the semiconductor device 13' is backbonded to the interpose...