Browse Prior Art Database

Tri State Amplifier

IP.com Disclosure Number: IPCOM000089767D
Original Publication Date: 1977-Dec-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 3 page(s) / 38K

Publishing Venue

IBM

Related People

Madyiwa, SP: AUTHOR

Abstract

This circuit combines the two outputs of a digital current-switch emitter-follower phase detector or comparator to give a single output which maintains the intelligence of the phase comparator. In Fig. 1, resistances R1 thru R7 each equal R and IR = VBE (base-to-emitter voltage of a conducting transistor).

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Tri State Amplifier

This circuit combines the two outputs of a digital current-switch emitter- follower phase detector or comparator to give a single output which maintains the intelligence of the phase comparator. In Fig. 1, resistances R1 thru R7 each equal R and IR = VBE (base-to-emitter voltage of a conducting transistor).

The circuit operates as follows for the various inputs:

1) If input A is up (logic 1) and input B is down (logic 0). current I flows through R1 and T1, bringing node N1 to a potential of VCC-VBE and node N2 to a potential of VCC-2VBE, and T4 is off. Current I flows through R4 and T5. T6 is off. Current I flows through R5 and T7. Node N3 is at VCC-VBE, node N4 is at VCC-2VBE, and T9 is off. Current I flows through R4 and T10. Thus, current 21 flows through R4, and node N4 is at a potential of VCC-2VBE.

If input B goes up while input A is up, current I flows through R5 and T6. T7 goes off, and node N3 is at VCC. Node N4 is at VCC-VBE. Current I flows through R7 and T9, and T10 is off. Since input A is still up, current I flows through R4 and T5. Thus node NC goes to a potential of VCC-VBE. As long as input A is up and input B varies between logic 1 and logic 0, node NC will vary between VCC-VBE and VCC = 2VBE.

2) When input A is down and input B is up, T1 is off, and node N1 is at VCC. T3 and T4 are on, and current 1 flows through R3 and T4. No current flows through T5. T6 is on, and T7 is off.

T8 and T9 are on, and current I flows through R7 and T9. T10 is off. Thus, no current flows through R4. Node NC is at a potential of VCC. When input A goes up (input B is still up), node N1 goes to VCC-VBE, T3 and T4 go off, and current I flows through R4 and R5. Node NC goes to a potential of VCC-VB...