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Browse Prior Art Database

SDLC/X.21 Converter

IP.com Disclosure Number: IPCOM000089777D
Original Publication Date: 1977-Dec-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 3 page(s) / 62K

Publishing Venue

IBM

Related People

Nelson, PE: AUTHOR [+3]

Abstract

The relatively new CCITT and ANSI recommended X.21 digital network has a connection protocol which utilizes a line code form similar to USASCII, BSC (Binary Synchronous Communication). Devices which are designed to operate in SDLC (Synchronous Data Link Control) line discipline only are presented with a number of incompatibilities which preclude a straight-forward connection.

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SDLC/X.21 Converter

The relatively new CCITT and ANSI recommended X.21 digital network has a connection protocol which utilizes a line code form similar to USASCII, BSC (Binary Synchronous Communication). Devices which are designed to operate in SDLC (Synchronous Data Link Control) line discipline only are presented with a number of incompatibilities which preclude a straight-forward connection.

This article describes a comparatively simple converter which will permit an SDLC device designed to work with an RS-232 interface to connect to the X.21 interface. The converter utilizes the fact that two or more USASCII synchronizing characters (X'16') are used by the X.21 network to establish character synchronization for call establishment. The first of the two or more synchronizing characters is used to condition the converter to encode and pass on to the SDLC device an SDLC flag sequence (X'7E') on the occurrence of a second contiguous synchronizing character and subsequently received contiguous synchronizing characters.

When the first following nonsync character is detected by the converter, it is passed on as data (call progress and status data) to be recognized by the SDLC receiver. Because SDLC is an inherently transparent discipline for data, the converter provides the capability of inserting the required zero bit at the occurrence of five contiguous ones detected in the X.21 call establishment data stream, permitting the data to be received by the SDLC device as true SDLC data. An additional shortened clock pulse is generated by the converter at the appropriate time to allow for the insertion of the zero bit, such that actually two clock pulses are received by the SDLC receiver in a single bit time of the X.21 provided clock. The converter will recognize the various defined end-delimiting characters and will cause the data to the SDLC receiver to be forced to an all one's condition, a natural end delimiter for SDLC. No checking is defined for the
X.21 protocol; hence, the all one's character implying an aborted SDLC frame is an acceptable end delimiter.

Once the X.21 network information is provided in SDLC form by the converter, it is intended that the SDLC device will properly handle the remainder of the connection sequence until the connection is fully established.

The connection is complete when the interface indication signal is detected, at which time the converter b...