Browse Prior Art Database

Memory Wait Stops Microprocessor While Memory Cycle Occurs

IP.com Disclosure Number: IPCOM000089782D
Original Publication Date: 1977-Dec-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 29K

Publishing Venue

IBM

Related People

Heuer, DA: AUTHOR [+4]

Abstract

The microprocessor 2 or other user of memory 3 has a single instruction input which, when valid, causes the microprocessor to cease instruction execution at the termination of the current instruction cycle. As shown in the figure, the control line 4 from the memory control, which requests a memory cycle, also sets a latch 5, which causes an output in the set condition that brings the single cycle input to a valid condition. Upon completion of the memory cycle, the control line 6, which indicates to the memory control 7 that such cycle has been completed, also resets latch 5.

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Memory Wait Stops Microprocessor While Memory Cycle Occurs

The microprocessor 2 or other user of memory 3 has a single instruction input which, when valid, causes the microprocessor to cease instruction execution at the termination of the current instruction cycle. As shown in the figure, the control line 4 from the memory control, which requests a memory cycle, also sets a latch 5, which causes an output in the set condition that brings the single cycle input to a valid condition. Upon completion of the memory cycle, the control line 6, which indicates to the memory control 7 that such cycle has been completed, also resets latch 5.

Using this circuitry in conjunction with the memory control circuitry causes a constraint to be placed on the microprocessor which will inhibit the next instruction cycle if the memory cycle has not been completed. However, if such memory cycle has been completed prior to the next instruction, the single instruction signal will be removed, and the microprocessor will be unaware that any potential constraint had been present. Use of this technique permits the microprocessor or other memory user to utilize any memory without the necessity of requiring the memory to be fast enough to assure cycle completion within the time required by the user. The scheme may also be used to overcome irregular delays in the access to memory induced by the contention between several users of the same memory,

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