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Shared Adder Yields High Performance Low Circuit Count Counter

IP.com Disclosure Number: IPCOM000089783D
Original Publication Date: 1977-Dec-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Related People

Heuer, DA: AUTHOR [+2]

Abstract

In the counter circuit shown in the figure, bistable latch or polarity hold (PH) circuits 3, 4 have been substituted for triggers which are commonly used in the art. Adders 5 and 6 are connected to the outputs of polarity holds 3 and 4, respectively.

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Shared Adder Yields High Performance Low Circuit Count Counter

In the counter circuit shown in the figure, bistable latch or polarity hold (PH) circuits 3, 4 have been substituted for triggers which are commonly used in the art. Adders 5 and 6 are connected to the outputs of polarity holds 3 and 4, respectively.

By using AND-OR-Invert (AOI) blocks 7 and 8 and adding a new register in the form of polarity holds 11, 12, 13, 14, two counters are generated using the same adder circuits 5 and 6. This scheme for dual use of the adder circuits provides a shared adder design which affords high performance in conjunction with a low circuit count. Additional polarity hold circuits may be added in parallel with polarity holds 11, 12, 13, 14 to also share the adder circuits 5 and 6 and adder polarity hold circuits 3 and 4, and further reduce the circuit count required for each counter function.

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