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Sample And Hold Test Gating Technique

IP.com Disclosure Number: IPCOM000089784D
Original Publication Date: 1977-Dec-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

Iverson, JH: AUTHOR [+2]

Abstract

The advent of large-scale integration (LSI) technology has resulted in an increased quantity of logic at the first level package. This increased circuit density has greatly increased the circuit-to-pin ratios. This logic package must be tested when manufactured, and where the logic is sequential in nature, the testing problem is also increased.

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Sample And Hold Test Gating Technique

The advent of large-scale integration (LSI) technology has resulted in an increased quantity of logic at the first level package. This increased circuit density has greatly increased the circuit-to-pin ratios. This logic package must be tested when manufactured, and where the logic is sequential in nature, the testing problem is also increased.

Experience has shown that testability can be enhanced by the addition of input test signals that provide such functions as resetting certain registers, setting counters and inhibiting clocks. Often, however, signal pins that can be used strictly for testing are either limited in number or do not exist. The technique described below is a method of combining a functionally mutually exclusive input and an output in a sample-and-hold manner to set a test state latch. This latch may then be used to gate numerous signals, for instance, a data bus to generate a number of unique test conditions.

The sample-and-hold latch may be implemented as shown in Fig. 1. The sample signal is the power-on reset (POR) which resets most of the memory elements within the chip that is the logic package of concern and includes the instruction address register (IAR). If one of the bits of the IAR, shown as IAR bit X, which is functionally an output, is brought back into the chip as an input using only one signal pin, that signal then becomes a common input-output (CIO). If this pin is forced down (active) as an...