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Dual Threshold Peak Detector Circuit

IP.com Disclosure Number: IPCOM000089801D
Original Publication Date: 1977-Dec-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 31K

Publishing Venue

IBM

Related People

Harr, JD: AUTHOR

Abstract

The peak detector circuit is arranged to have a relatively high threshold voltage as the signal with noise approaches a peak value and, thereafter, to switch to a relatively low threshold voltage, whereby the desired timing information is accurately sensed.

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Dual Threshold Peak Detector Circuit

The peak detector circuit is arranged to have a relatively high threshold voltage as the signal with noise approaches a peak value and, thereafter, to switch to a relatively low threshold voltage, whereby the desired timing information is accurately sensed.

A dual-threshold voltage is effected by modifying the threshold voltage V(th) applied to the amplifying circuit A(2). When the analog input signal is in the vicinity of its noisiest region (the negative peak in this example), then the latch output is down, forward biasing D(3). By the action of the R(1) - R(2) voltage divider, the threshold voltage applied to the noninverting input of A(2) is lowered, thereby requiring a larger signal reversal to set the latch. Once this region is passed and the latch has been set, D(3) is reverse-biased, and the threshold voltage is applied to A(2) for use during the positive peaks. Thus the threshold, and hence the noise sensitivity, has been modified to a new value for the negative portions of the input waveform.

The diode D(3), from the digital output to the threshold input of one of the amplifiers, actually is not required for proper operation. All that is really required is that the digital output change the threshold voltage as it changes from one state to another.

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