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Twin Cell Layout for High Speed Random Access Memory

IP.com Disclosure Number: IPCOM000089827D
Original Publication Date: 1977-Dec-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Rideout, VL: AUTHOR [+2]

Abstract

A circuit for a two-device memory cell is shown in Fig. 1. This circuit can be used advantageously for differential sensing. The two field-effect transistor (FET) source nodes each contact a side of the storage capacitor. This can create some fabrication and layout difficulties. For example, the metal word line may react capacitively with the storage capacitor. This can be a critical problem in a differential sensing scheme. Another problem is that the cell area may become relatively large due to an etched contact hole between the n+ FET drain and the polysilicon capacitor electrode.

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Twin Cell Layout for High Speed Random Access Memory

A circuit for a two-device memory cell is shown in Fig. 1. This circuit can be used advantageously for differential sensing. The two field-effect transistor (FET) source nodes each contact a side of the storage capacitor. This can create some fabrication and layout difficulties. For example, the metal word line may react capacitively with the storage capacitor. This can be a critical problem in a differential sensing scheme. Another problem is that the cell area may become relatively large due to an etched contact hole between the n+ FET drain and the polysilicon capacitor electrode.

Shown in Fig. 2 is a layout that decouples the metal word line from the storage capacitor without sacrificing area. The key to the layout is to run the metal word line over the storage capacitor of an adjacent cell, rather than over the storage capacitor of the cell being addressed. A buried contact is used to connect the source of one FET to the polysilicon storage plate of the storage capacitor. The buried contact, which is a well-known technique, is in effect a self- registering contact between n+ diffusion and polysilicon, and is small in area. A second but somewhat more elaborate scheme is shown in Fig. 3, which uses two polysilicon layers. The second polysilicon layer serves as a field plate to screen the capacitor from the metal bit lines. In both cases conventional polysilicon gate processes common in the industry are utili...