Browse Prior Art Database

Associated Memory

IP.com Disclosure Number: IPCOM000089866D
Original Publication Date: 1968-Dec-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 27K

Publishing Venue

IBM

Related People

Bidwell, AW: AUTHOR

Abstract

Array 2 of monolithic storage cells is controlled by a switch to provide associative addressing. Array 2 includes conventional three-dimensional addressing circuits, not shown, that permit addressing one word or individual cells of a word. Different words of an array can be addressed sequentially. Several arrays are provided for simultaneously addressing a number of words. Within each array, wires 4 and 5 are connected to each cell to carry signals for writing 1 or 0 and for sensing 0 or 1 respectively.

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Associated Memory

Array 2 of monolithic storage cells is controlled by a switch to provide associative addressing. Array 2 includes conventional three-dimensional addressing circuits, not shown, that permit addressing one word or individual cells of a word. Different words of an array can be addressed sequentially. Several arrays are provided for simultaneously addressing a number of words. Within each array, wires 4 and 5 are connected to each cell to carry signals for writing 1 or 0 and for sensing 0 or 1 respectively.

The switch includes transistors 6...9 that are connected to conduct signals from either wire 4 or 5 to sense circuits 10 or 11. The transistor base terminals receive signals from a bit drive circuit 12 and wires 13 and 14. Circuit 12 is common to several arrays, as the dashed lines indicate. Lines 13 and 14 are individual to each array and permit addressing particular arrays for a read or write operation.

Circuit 10 is common to the arrays and receives signals from the addressed array during a read operation. Circuit 11 is individual to each array and receives any mismatch signal during an associative addressing operation.

An associative search operation takes place in two steps. In one step, the cells to be searched for a 1 are conventionally addressed. Driver 12 controls the switch to transmit any mismatch signifying signals on wire 4 to be transmitted to circuit 11. A similar step causes any mismatch signal from the remaining storage cells to...