Browse Prior Art Database

Read Only Store Address Tracer

IP.com Disclosure Number: IPCOM000089916D
Original Publication Date: 1968-Dec-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 46K

Publishing Venue

IBM

Related People

Williams, CT: AUTHOR

Abstract

The apparatus traces the sequence of addresses applied to the read-only store ROS when that store is used to carry out the steps of a microprogram. If the controls associated with ROS malfunction, analyzing and repairing the malfunction is difficult without knowing the sequence of microprogram steps which precede the malfunction. The sequence of steps is determined by the sequence of addresses applied by the read-only address register ROA to the ROS. The ROA Tracers are employed to record the sequence of addresses.

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Read Only Store Address Tracer

The apparatus traces the sequence of addresses applied to the read-only store ROS when that store is used to carry out the steps of a microprogram. If the controls associated with ROS malfunction, analyzing and repairing the malfunction is difficult without knowing the sequence of microprogram steps which precede the malfunction. The sequence of steps is determined by the sequence of addresses applied by the read-only address register ROA to the ROS. The ROA Tracers are employed to record the sequence of addresses.

ROA Tracers 1...N are connected to output bus 1 which is connected between ROA and ROS. Since bus 1, in the example given, is twelve bits wide, the ROA Tracers, one is shown in detail in connection with ROA Tracer N, consist of a plurality of stages for each of the bit positions Bit O...bit 11. For example, with reference to Bit 0, M+1 stages S0...SM are shown. Similarly, each of the other Bit lines include corresponding stages 1SO...1SM for Bit 1, and so on for each Bit line not shown but indicated by dotted lines 2.

In each cycle in which an address is read from the ROA onto bus 1, the output is first stored in the appropriate stages of the Tracer 1 and then in subsequent Tracers until Tracer N is reached. For example, the output on the Bit 0 line for the first cycle is stored in the SO stage of Tracer 1. In the second cycle, the Bit 0 output is stored in S0 and the output of the previous cycle is stored in S1.

The step...