Browse Prior Art Database

Data Bit Error Detection

IP.com Disclosure Number: IPCOM000089928D
Original Publication Date: 1968-Dec-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 52K

Publishing Venue

IBM

Related People

Franchini, RC: AUTHOR [+2]

Abstract

During the write mode of a data processing system, precompensation is effected by an error detection circuit. Serialized input data is applied to shift register 10, drawing 1, that receives a transfer drive signal from oscillator 12 through trigger 14. The data is detected by error detection circuit 16 to determine if the data bits are early or late. Each data bit cell is split into two time intervals. Decoder 18 provides precompensation according to the bit pattern surrounding the bit being written.

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Data Bit Error Detection

During the write mode of a data processing system, precompensation is effected by an error detection circuit. Serialized input data is applied to shift register 10, drawing 1, that receives a transfer drive signal from oscillator 12 through trigger 14. The data is detected by error detection circuit 16 to determine if the data bits are early or late. Each data bit cell is split into two time intervals. Decoder 18 provides precompensation according to the bit pattern surrounding the bit being written.

Pulse former 20 produces data strobe pulses which are applied to generator 22 that develops clock and data strobes. These strobes are delayed in circuit 24 and Anded in 26 with the decoded output to enable write data compensation. One error detection circuit is shown in drawing 2. Gating logic determines the compensation for the early or late bits. Early decode 28 and late or on-time data 30 open And 32 to set latch 34. Similarly, late decode 36 and early or on-time data 38 open And 40 and set latch 34.

Another error detection circuit indicates the loss of a data bit. The compensated write data and the register 10 output are applied through And 42, drawing C, to set latch 44 to show that a data bit is present at the output of And
26. Latch 44 inactivates And 46. The inputs from register 10 and strobe former 20 are applied to And 46. If the data bit is absent, then latch 44 is not set and the three-input And 46 sets latch 48 to indicate a miss...