Browse Prior Art Database

Field Effect Transistor

IP.com Disclosure Number: IPCOM000089955D
Original Publication Date: 1968-Dec-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 43K

Publishing Venue

IBM

Related People

Baker, AR: AUTHOR [+3]

Abstract

This structure is for improving the stability of N- and P-channel metal over silicon field effect transistors. Field effect transistor 10 has N-type source and drain regions 12 and 14 formed by diffusing an N-type impurity into a P-type monocrystalline semiconductor wafer 16. Metal terminals or electrodes 18 and 20 are in electrical contact with the regions 12 and 14. Gate electrode 22 is located over the space between regions 12 and 14 and is insulated by a layer 24 of thermally grown SiO(2), an intermediate sputtered silicon nitride layer 26, and a top layer 28 of sputtered silicon SiO(2). Layers 24, 26, and 28 have a thickness of approximately 400 angstroms. The purpose of layer 24 is to provide a reproducible low surface state density and hence a reproducible threshold voltage and frequency response.

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Field Effect Transistor

This structure is for improving the stability of N- and P-channel metal over silicon field effect transistors. Field effect transistor 10 has N-type source and drain regions 12 and 14 formed by diffusing an N-type impurity into a P-type monocrystalline semiconductor wafer 16. Metal terminals or electrodes 18 and 20 are in electrical contact with the regions 12 and 14. Gate electrode 22 is located over the space between regions 12 and 14 and is insulated by a layer 24 of thermally grown SiO(2), an intermediate sputtered silicon nitride layer 26, and a top layer 28 of sputtered silicon SiO(2). Layers 24, 26, and 28 have a thickness of approximately 400 angstroms. The purpose of layer 24 is to provide a reproducible low surface state density and hence a reproducible threshold voltage and frequency response. The purpose of intermediate layer 26 is to provide the barrier for ionic drift and increase gate capacitance. Top layer 28 is provided to reduce the injection of charge into layer 26 and hence reduce the overall electric field in the gate insulator when gate electrode 22 is biased. Layers 26 and 28 can be deposited by pyrolytic processes. The same composite three-layer insulation can be used to insulate the remaining portions of the device.

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