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Data Synchronization Method

IP.com Disclosure Number: IPCOM000089978D
Original Publication Date: 1968-Dec-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 36K

Publishing Venue

IBM

Related People

Donnan, RA: AUTHOR

Abstract

In the sampling of signals present on a transmission line, it is desirable to take the sample at about the middle of a signal pulse. The purpose is to select the most reliable point for data and to allow the maximum range over which the sampling clock can drift during periods of signalling without a voltage transition. This synchronization method allows the receiver clock to drift relative to the transmit clock. Receive clock corrections are made only when the sampling time approaches too closely to the transition points of a signal.

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Data Synchronization Method

In the sampling of signals present on a transmission line, it is desirable to take the sample at about the middle of a signal pulse. The purpose is to select the most reliable point for data and to allow the maximum range over which the sampling clock can drift during periods of signalling without a voltage transition. This synchronization method allows the receiver clock to drift relative to the transmit clock. Receive clock corrections are made only when the sampling time approaches too closely to the transition points of a signal.

A signal input on terminal 1 is one input of And 2 which passes samples of the signal to a data processor. The sample is gated by a signal on line 5 from clock decoder 4. Clock 5, comprising five binary stages, is driven by pulses from oscillator 6 through clock control circuit 7. The latter can be set by a signal on line 8 to add a clock driving pulse or can be set by a signal on line 9 to block passage of one pulse from oscillator 6. Normally, decoder 4 is so wired that the signal on terminal 1 is sampled at a count of eight in clock 5.

To insure that sampling of a signal does not take place in the disturbed zones just before or just after a signal voltage transition on line 1, clock 5 is corrected if sampling is too close to the transition. Signal transition detector 10 for positive- going transitions and detector 11 for negative-going transitions are connected to terminal 1. Each gives an output signal...