Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Shared Parity Checker

IP.com Disclosure Number: IPCOM000089979D
Original Publication Date: 1968-Dec-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 46K

Publishing Venue

IBM

Related People

Low, K: AUTHOR

Abstract

In some data processing machines, it is often desirable to identify to the system a register which initiates a data transmission found to be in error. In machines where a common data bus is provided, a detected parity error cannot be immediately ascribed to a specific source unless a parity checker is connected to each source. In this arrangement, a plurality of data registers A...N is connected through gates 4, 5, 6, etc., to supply their stored data to common transmission bus 7. Each register A...N contains a parity bit position 8. When the associated register data is gated out to bus 7, the parity bit position is gated through a gate 9 to common parity lead 10. Register selector 11 is activated by the machine programs to select the registers A...

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 79% of the total text.

Page 1 of 2

Shared Parity Checker

In some data processing machines, it is often desirable to identify to the system a register which initiates a data transmission found to be in error. In machines where a common data bus is provided, a detected parity error cannot be immediately ascribed to a specific source unless a parity checker is connected to each source. In this arrangement, a plurality of data registers A...N is connected through gates 4, 5, 6, etc., to supply their stored data to common transmission bus 7. Each register A...N contains a parity bit position 8. When the associated register data is gated out to bus 7, the parity bit position is gated through a gate 9 to common parity lead 10. Register selector 11 is activated by the machine programs to select the registers A...N for data transfer by energization of a control line such as 12, 13, 14, etc. An energized control line opens a gate such as 4 and its associated gate 9 to apply the register data to bus
7. Parity generator 15 connected to bus 7 then generates on its output 16 the parity of the transmitted data. Exclusive-Or 17 compares the parities on lines 10 and 16. If any error is found, error line 18 is energized. Each register selecting lines 12, 13, 14, etc., is also one input of a corresponding And 19 which has line 18 as its other input. Each And 19 has its output connected to the set input of a corresponding latch 20. A common reset line, connected to all latches 20, is energized to return the system to...