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Start Clock Circuit

IP.com Disclosure Number: IPCOM000089988D
Original Publication Date: 1969-Jan-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 29K

Publishing Venue

IBM

Related People

Gutierrez, LH: AUTHOR

Abstract

This timing wave gating circuit does not require phase-selecting circuitry. Sine-wave high-frequency oscillator 10 is coupled in series with one or more Inverters 12 and 14. These are coupled to Exclusive-Or 18 for producing a train of sharp pulses at twice the frequency of Or 18 for producing a train of sharp pulses at twice the frequency of oscillator 10. The pulses are applied to flip-flop 20 of the gated type for producing a clock pulse train at output terminals 22. Flip-flop 20 is gated on for each incoming character by the application of a synchronizing pulse at input terminal 24 to a latch comprising And's 26 and 28.

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Start Clock Circuit

This timing wave gating circuit does not require phase-selecting circuitry. Sine-wave high-frequency oscillator 10 is coupled in series with one or more Inverters 12 and 14. These are coupled to Exclusive-Or 18 for producing a train of sharp pulses at twice the frequency of Or 18 for producing a train of sharp pulses at twice the frequency of oscillator 10. The pulses are applied to flip-flop 20 of the gated type for producing a clock pulse train at output terminals 22. Flip- flop 20 is gated on for each incoming character by the application of a synchronizing pulse at input terminal 24 to a latch comprising And's 26 and 28.

A reset pulse at the end of each character is applied at input terminal 30 to the latch for gating off flip-flop 20.

Thus, the clocking pulse train generated is gated on and off so closely after the synchronizing and reset pulse of each character appear at the terminals 24 and 30 respectively that the individual bits are translated without distortion.

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