Browse Prior Art Database

Core Storage Addressing

IP.com Disclosure Number: IPCOM000089989D
Original Publication Date: 1969-Jan-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 26K

Publishing Venue

IBM

Related People

Cordero, H: AUTHOR

Abstract

Data processing systems customarily utilize arithmetic and logic circuits which operate on words comprising a plurality of bytes. Such systems generally have a storage unit 1 in which the unit of storage is less than a word, for example, a byte. Before a word can be processed several storage cycles are necessary so that the entire word is available.

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Core Storage Addressing

Data processing systems customarily utilize arithmetic and logic circuits which operate on words comprising a plurality of bytes. Such systems generally have a storage unit 1 in which the unit of storage is less than a word, for example, a byte. Before a word can be processed several storage cycles are necessary so that the entire word is available.

In this device, the first byte of information is read from storage unit 1 and placed on bus 2, having a separate line for each of the eight bits in a byte. The first byte of a word is loaded into eight-bit register 3 through And 4 which is conditioned by a first byte timing signal.

The second byte is then read from storage 1 and placed on bus 2. A second byte signal conditions And 5 to connect both the eight-bit bus 2 and the eight outputs from register 3 onto bus 6 which is two bytes wide. In this manner, a single eight-bit buffer accommodates the parallel transfer of two bytes of data from storage to other elements of the system.

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