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Sample and Hold Circuit

IP.com Disclosure Number: IPCOM000089998D
Original Publication Date: 1969-Jan-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 31K

Publishing Venue

IBM

Related People

Gambrel, DR: AUTHOR

Abstract

Sample and hold circuits are normally restricted as to hold time duration by leakage currents which cause decay. This circuit overcomes the leakage problems and holds for a long time.

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Sample and Hold Circuit

Sample and hold circuits are normally restricted as to hold time duration by leakage currents which cause decay. This circuit overcomes the leakage problems and holds for a long time.

Initially, field effect transistors Q1, Q2, and Q3 are off and field effect transistor Q4 is on. The output of comparator A2 is at a down level since Vo, the negative input, is greater than the V1, the positive input to comparator A2. The latter is such that when the positive input is greater than the negative input, the output is at an up level. When the negative input is greater than the positive input, the output is at a down level. At time T0, the Reset pulse is turned on causing Q1 to turn on discharging capacitor C and causing the output of operational amplifier A1 to approach V2. Since V2 must be greater than V11 the output of comparator A2 remains at a down level causing Q2 to remain off. At time T1, the Reset pulse is turned off which turns Q1 off allowing amplifier A1 and C to hold Vo equal to V2 from time T1 until time T2.

At time T2, the sample pulse is turned on causing Q3 to switch on and Q4 to go off thus applying Vi to the positive input of comparator A2 in place of V1. The output of comparator A2 then rises to the up Level which switches Q2 to the on state, thus connecting resistor R to the minus input of amplifier A1. This results in forming an integrator of R, C, and amplifier A1. Voltage V3 is integrated linearly until Vo becomes slightly...