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Computer Fault Generator

IP.com Disclosure Number: IPCOM000090007D
Original Publication Date: 1969-Jan-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 3 page(s) / 49K

Publishing Venue

IBM

Related People

Cormier, RL: AUTHOR [+3]

Abstract

This fault generator generates simulated intermittent or solid hardware failures in a data processing system. Such failures are used to test error recovery programs or error-detection circuitry.

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Computer Fault Generator

This fault generator generates simulated intermittent or solid hardware failures in a data processing system. Such failures are used to test error recovery programs or error-detection circuitry.

Fault generator 2 responds to a sync pulse which is inverted by Inverter 14 and applied to fire successive single-shots S-S's 6, 8, 10, and 12. The outputs of such single-shots are selectively picked off by delay switch 14 and applied to fire single-shot 16. Thus there is a selective delay of the sync pulse of .5, 1.5, 2.5,
3.5 or 4.5 microseconds before setting latch 18. This remains set until manually reset by activating switch 20. In being set, latch 18 provides a positive level transition output. The latter is used via Indicator Driver 1D28 to turn on indicator 30 indicating the set condition of latch 18, via Inverter 132 to provide a negative level transition signal as a solid fault signal and to fire a 600 nanosecond single- shot S-S34 which applies a negative pulse via Inverters 136 and 138 as an intermittent fault signal. The general logic configuration shown is applicable to all data processing systems. The particular type of logic that is required has to be compatible with that of the data processing system under test.

In operation, the input to generator 2 is connected to a selectable sync point in the data processing system such as, for example, the storage address compare point. At such point a sync pulse is generated whenever a storage reference is made to an address specified by the console 44 address switches. The fault output of generator 2 can be connected to any one of a variety of error points in the system. Such points are, for example, a stage of a data register, an adder, a counter, etc., which are involved in the execution of the instruction located at the specified storage address. The setting of switch 14 is set to provide a delay period for the sync pulse. Such periods comparable to the time period between fetching the selected instruction from the specified storage address to the appearance of an operand at the error point in the execution of the selected instruction. Thus the fault can be injected in time with the appearance of the operand at that point.

In intermittent error operation, the input of generator 2 can be connected to the output of the storage address compare 40. The intermittent fault output can be connected to a stage of adder 42. Switch 14 is set to an appropriate setting in accordance with the selected instruction and error point. The specified address is set into the console 44 address switches, switch 20 is actuated to insure resetting of latch 18, thus conditioning generator 2 for operation, and the program can now be run. When the selected instruction is reached, a sync pulse is generated and applied to generator 2 where it is effective to turn on indicator 30 and to inject a fault in the selected stage of adder 42. The injected fault causes an error. This is detect...