Browse Prior Art Database

Fixed Head File Error Correction

IP.com Disclosure Number: IPCOM000090009D
Original Publication Date: 1969-Jan-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 3 page(s) / 60K

Publishing Venue

IBM

Related People

Dauber, PS: AUTHOR [+3]

Abstract

This error-detection and correction method is for a system in which records are stored serially by byte, one bit of each byte recorded on an individual track on an individual surface of a storage media such as a disk storage. A defect in a surface can cover several bit positions and, with less likelihood, several tracks. A record uses only one track on a surface and, therefore, a single defect can effect only corresponding bit positions in successive bytes. A number of interleaved single-error-correcting, double-error-detecting, Hamming codes are used, the particular number used determining the length of error which can be corrected. A total of (n + 2) check bits, P0...P(n+1) can be used to cover from 2/n/ up to (2/n+1/-1) message bits.

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Fixed Head File Error Correction

This error-detection and correction method is for a system in which records are stored serially by byte, one bit of each byte recorded on an individual track on an individual surface of a storage media such as a disk storage. A defect in a surface can cover several bit positions and, with less likelihood, several tracks. A record uses only one track on a surface and, therefore, a single defect can effect only corresponding bit positions in successive bytes. A number of interleaved single-error-correcting, double-error-detecting, Hamming codes are used, the particular number used determining the length of error which can be corrected. A total of (n + 2) check bits, P0...P(n+1) can be used to cover from 2/n/ up to (2/n+1/-1) message bits. This may represent an additional check bit over and above that required for the usual Hamming method but allows the error syndrome generated to directly indicate the address of the message bit in error. Also, one further check bit Px is used to provide double-error-detection capability.

In 1A, a simple example of the way the check bits cover the data bits to form a check word for a message with a maximum length of sixteen data bits is shown. The double-error-detection bit Px is the odd parity of every bit including all check bits. Bits P0...P5 form parity on the data bits as shown. P5 is the additional check bit over and above that required for the usual Hamming method. As an example of parity generation, bit DO enters into parity calculation of all of check bits P0...P5. Data bit D1 enters into parity calculation for check bits P1...P5, and so on. Due to the additional check bit P5, each data bit contributes to the parity calculation in positions corresponding to the 1's in the one's complement of its address. For example, D1 contributes to the parity calculation in positions P1, P2, P3, P4, and P5 but not P0. If D1 is in error, the error syndrome is 111110. The one's complement of its address is 000001. Errors in any data bit position operate similarly. Errors in parity bits indicate addresses sixteen or greater. As an example, a message of sixteen data bits is transmitted, as in B with bits D9...D15 assumed zero. The check word, Px omitted, for this message is 001001 and is transmitted along with the message. If the message is received with D1 in error, for example, then the check word recalculated from the message received in error is 110111. The modulo-2 sum of the transmitted check word and the calculated check word is 111110 which is the inverse of a binary 1, therefore indicating that the error is in message position D1.

Interleaving, as in C, is based on the assumption of a maximum record leng...