Browse Prior Art Database

Monolithic Latching Photodetector Array

IP.com Disclosure Number: IPCOM000090026D
Original Publication Date: 1969-Jan-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 79K

Publishing Venue

IBM

Related People

Curtis, JJ: AUTHOR [+2]

Abstract

This monolithic latching photodetector array combines a plurality of light sensitive circuits into a single matrix. Each individual cell of the matrix, as at A, contains a lateral PNP phototransistor with a large P area that is photosensitive and the associated latching circuits. The array of cells can be interrogated electrically a word, row, at a time or can be all reset or cleared at once as the result of a clear pulse. After the clear pulse is applied, the matrix is again activated via a new set of illuminated light spots. Correlation between the chip structure at A and the circuit at B is indicated by matching designations.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 88% of the total text.

Page 1 of 2

Monolithic Latching Photodetector Array

This monolithic latching photodetector array combines a plurality of light sensitive circuits into a single matrix. Each individual cell of the matrix, as at A, contains a lateral PNP phototransistor with a large P area that is photosensitive and the associated latching circuits. The array of cells can be interrogated electrically a word, row, at a time or can be all reset or cleared at once as the result of a clear pulse. After the clear pulse is applied, the matrix is again activated via a new set of illuminated light spots. Correlation between the chip structure at A and the circuit at B is indicated by matching designations.

A negative pulse, applied to the clear drive line at B and C, is distributed to all the cells on the chip to reset them to the state where the common collector T2C of transistor pair T2 is on, corresponding to the 0 state. During this resetting the word drive lines are held at 0 volts. After resetting the matrix to its normal condition, selected photocell sections P3 are illuminated in accordance with a particular storage pattern. The output from the illuminated photocells is amplified by transistor T4 to turn on the transistor pair T5 indicating a 1 state.

Readout of the memory occurs when a positive pulse is applied to the word drive line causing a current to flow in sense line 6 which terminates at ground in sense amplifier 7. If the cell is not illuminated, that is, transistor pair T5 is not tur...