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Programmable Time Base Generator

IP.com Disclosure Number: IPCOM000090027D
Original Publication Date: 1969-Jan-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

Holmstrom, LW: AUTHOR

Abstract

An oscillator counter, compare logic, and data registers with appropriate controls associated with a digital computer eliminates the problems of both the program loop method and the internal timer method when generating accurate timing pulses from a digital computer to operate external devices. The operation of this system is as follows. The counter is driven by a free-running oscillator which has any reasonable frequency. The counter is reset to the zero status by the computer. The count of the first time period required is written by the computer into the compare register. The computer then returns to other processing requirements.

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Programmable Time Base Generator

An oscillator counter, compare logic, and data registers with appropriate controls associated with a digital computer eliminates the problems of both the program loop method and the internal timer method when generating accurate timing pulses from a digital computer to operate external devices. The operation of this system is as follows. The counter is driven by a free-running oscillator which has any reasonable frequency. The counter is reset to the zero status by the computer. The count of the first time period required is written by the computer into the compare register.

The computer then returns to other processing requirements.

When the counter reaches the status of the compare register, the computer is interrupted. This same pulse which interrupts the computer is also sent out to control external devices. When the computer is interrupted, the next compare status is written into the compare register. The computer then proceeds with other processing. Again, when the counter reaches the compare register status, the computer is interrupted. This process continues for each time period required. The counter is allowed to run free. When the highest count is reached it returns to the zero state and then continue counting upward again. This can be taken into consideration in the computer by ignoring any arithmetic overflows concerned with add instructions used to generate the next compare field.

Since the counter is free-running, it...