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FET Diode Stored Charge Memory Cell

IP.com Disclosure Number: IPCOM000090055D
Original Publication Date: 1969-Jan-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 27K

Publishing Venue

IBM

Related People

Gaensslen, FH: AUTHOR

Abstract

Drawing A shows a stored charge memory cell employing two N-channel enhancement mode FET's Q1 and Q2 and two diodes D1 and D2. The pulse pattern for operating the N-channel cell is shown in drawing B.

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FET Diode Stored Charge Memory Cell

Drawing A shows a stored charge memory cell employing two N-channel enhancement mode FET's Q1 and Q2 and two diodes D1 and D2. The pulse pattern for operating the N-channel cell is shown in drawing B.

In drawing A, the memory cell consists of cross-coupled FET's Q1 and Q2 with diodes D1 and D2 coupled in series with Q1 and Q2 respectively. Quiescently, word line WL and bit lines BL1 and BL2 are all at ground potential. To write a binary 0 into the cell, BL1 and WL are changed to a negative potential -V while BL2 is held at ground potential. This pattern is shown in drawing B, reading vertically from W0. The voltage -V is somewhat larger than the substrate voltage -V Sub in order to retain a certain threshold of voltage. Reducing the voltage on the word line WL reduces the source to substrate voltage and thus the device thresholds. The voltages on the gates of FET's Q1 and Q2 appear at nodes N2 and N1 respectively. By applying the above-mentioned voltages, node N2 charges up via diode D2. The input capacitance of Q1, the coupling capacitance between node N1 and node N2 and the capacitance from node N2 to the substrate, is charged up. If the voltages on BL1 and WL1 are brought back up to ground potential, the potential on node N2 is pushed above ground. Because of this, diode D2 becomes backward biased. Until changed by the application of other potentials, the charge on node 2 is trapped and can only be removed as a leakage curre...