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Multiword Size Storage

IP.com Disclosure Number: IPCOM000090069D
Original Publication Date: 1969-Jan-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 3 page(s) / 40K

Publishing Venue

IBM

Related People

Gates, GA: AUTHOR [+3]

Abstract

Storage areas of different word widths can be combined into a unit S so as to avoid wastage or nonuse of storage bits due to the difference in word sizes. Storage area T has a capacity of c words of n bits. Storage area D has a capacity of c words of m bits, where m is greater than n. If such areas are combined into a single unit S, the resultant storage requires a width m equal to that of the larger word size. Thus, the shaded area W associated with the smaller word size area is unused or wasted. Two units S0 and S1 can be combined into a single unit TDU of a width m+n to avoid wasted storage space. This can be accomplished by alternating the T and D areas between the upper and lower halves of adjacent units S0 and S1.

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Multiword Size Storage

Storage areas of different word widths can be combined into a unit S so as to avoid wastage or nonuse of storage bits due to the difference in word sizes. Storage area T has a capacity of c words of n bits. Storage area D has a capacity of c words of m bits, where m is greater than n. If such areas are combined into a single unit S, the resultant storage requires a width m equal to that of the larger word size. Thus, the shaded area W associated with the smaller word size area is unused or wasted. Two units S0 and S1 can be combined into a single unit TDU of a width m+n to avoid wasted storage space. This can be accomplished by alternating the T and D areas between the upper and lower halves of adjacent units S0 and S1.

TDU is implemented in monolithic technology. TDU has m+n storage chips each with a capacity of 2 c bits. Each chip contains address decoding circuits, read-write control circuits, powering circuits for data in, and sense amplifiers plus one data latch for data out. TDU is arranged in three sections. The first section contains area T0 and bits 0...n-1 of area D0. The second section contains bits n...m-1 of areas D0 and D1. The third section contains area T1 and bits 0...n-1 of D1. Select signals are used to power up the various sections according to the particular area desired.

The drawing shows one way in which several TDU's can be combined to form a larger system in which the respective T and D sections may be selectively accessed. In the example, it is assumed that there are sixteen units S combined to form eight TDU's. Access requests for T sections are placed in an address register TAR. Access requests for the D sections are placed in an address register DAR. In the example, it is also assumed that each chip or section has 256 bit locations so as to provide for 256 words. In TAR and DAR, bits 0...3 are sent to select controls for generating the respective select signals for accessing the individual section. Bits 4...10 are used to select individual w...