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Browse Prior Art Database

Memory Store Control

IP.com Disclosure Number: IPCOM000090075D
Original Publication Date: 1969-Jan-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 30K

Publishing Venue

IBM

Related People

Ligon, GC: AUTHOR

Abstract

Or 3 and And 4 are interconnected to form a latch for holding data that is to be stored in a ferrite core 5 of a magnetic memory. The latch has an input 6 to And 4 that must carry a 1 to enable the latch to respond to its other inputs. An input 7 of Or 3 receives data from sense circuit 8 that is arranged to receive a signal produced by core 5 during a read operation. Or 3 has an input 9 that receives data on line 10 that is to be stored in the memory. The circuit receives a store signal on line 11 that conditions the circuit to respond to data input 10 when the store signal is a 1 or to respond to the circuit 8 output when the store signal is a 0.

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Memory Store Control

Or 3 and And 4 are interconnected to form a latch for holding data that is to be stored in a ferrite core 5 of a magnetic memory. The latch has an input 6 to And 4 that must carry a 1 to enable the latch to respond to its other inputs. An input 7 of Or 3 receives data from sense circuit 8 that is arranged to receive a signal produced by core 5 during a read operation. Or 3 has an input 9 that receives data on line 10 that is to be stored in the memory.

The circuit receives a store signal on line 11 that conditions the circuit to respond to data input 10 when the store signal is a 1 or to respond to the circuit 8 output when the store signal is a 0. The circuit is particularly useful for applications where a decision to store the new data 10 or to restore the existing data from sense circuit 8 cannot be made until after the memory cycle starts. A reset input 12 is also included. And 13 responds to store signal 11 to transmit data from line 10 to input 9 of Or 3 when new data is to be stored. When this is required store signal 11 is also transmitted to Or 14 and Inverter 15 to the reset input 6 of the latch. The output of Inverter 15 is combined in an Or function connection 16 with the output from And 13 which is transmitted through And 17. The latter isolates point 16 from line 9. The logic function provided by gates 15 and 17 at point 16 resets the latch if a decision to store is made after the latch has already responded to the output of sen...