Browse Prior Art Database

Current Balancing

IP.com Disclosure Number: IPCOM000090089D
Original Publication Date: 1969-Jan-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 27K

Publishing Venue

IBM

Related People

Gallo, JL: AUTHOR

Abstract

In this ferrite core memory array, cores 2 are located at the intersections of Y wires 3 and X wires 4 and 5. Although only one core is selected during a memory operation, wires 4 and 5 are driven in pairs so that the electrical noise associated with the X drive currents can be suppressed by differential sensing circuits not shown. For effective noise suppression, the currents in wires 4 and 5 are nearly equal. Transistors, 6...9 and resistors 11 and 12 are arranged to provide high current levels that are closely equal in wires 4 and 5. In response to a timing pulse, transistor 6 conducts in circuit with resistor 11 and wire 4 and transistor 7 conducts in circuit with resistor 11 and wire 5.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 2

Current Balancing

In this ferrite core memory array, cores 2 are located at the intersections of Y wires 3 and X wires 4 and 5. Although only one core is selected during a memory operation, wires 4 and 5 are driven in pairs so that the electrical noise associated with the X drive currents can be suppressed by differential sensing circuits not shown. For effective noise suppression, the currents in wires 4 and 5 are nearly equal. Transistors, 6...9 and resistors 11 and 12 are arranged to provide high current levels that are closely equal in wires 4 and 5. In response to a timing pulse, transistor 6 conducts in circuit with resistor 11 and wire 4 and transistor 7 conducts in circuit with resistor 11 and wire 5. Transistors 6 and 7 are formed as a common monolithic structure so that their electrical characteristics are closely similar and the currents in wires 4 and 5 are nearly equal. Transistors 8 and 9 are similarly formed as a common monolithic structure and provide equal currents in wires 4 and 5 in circuit with resistor 12. The circuit maintains low power dissipation in each chip.

1

Page 2 of 2

2

[This page contains 2 pictures or other non-text objects]