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Browse Prior Art Database

Etching Technique for Multilevel Metallurgy

IP.com Disclosure Number: IPCOM000090097D
Original Publication Date: 1969-Feb-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 53K

Publishing Venue

IBM

Related People

Tsui, RT: AUTHOR

Abstract

This technique is for controlling the depth of ion etching when applied to multilevel metallurgy. The action of an ion beam as an etchant is controlled or is self-limited by the application of a potential equal to that of the metallic cathode to a conductor which underlies an insulating layer which is being ion etched. This is accomplished by either a special conducting path around the edge of semiconductor wafer 1 or by a connection through wafer 1 itself. Thus, wafer 1 is shown disposed on the surface of metallic cathode 2. Wafer 1 has an oxide layer 3 overlying a surface of it and a layer characterized as a first metallization 4 disposed on the surface of layer 3.

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Etching Technique for Multilevel Metallurgy

This technique is for controlling the depth of ion etching when applied to multilevel metallurgy. The action of an ion beam as an etchant is controlled or is self-limited by the application of a potential equal to that of the metallic cathode to a conductor which underlies an insulating layer which is being ion etched. This is accomplished by either a special conducting path around the edge of semiconductor wafer 1 or by a connection through wafer 1 itself.

Thus, wafer 1 is shown disposed on the surface of metallic cathode 2.

Wafer 1 has an oxide layer 3 overlying a surface of it and a layer characterized as a first metallization 4 disposed on the surface of layer 3. Portions of layer 3 have apertures 5 into which a portion of metallization 4 extends to act as an electrical contact to active area 6 diffused or alloyed into wafer 1. A layer of dielectric insulation 7 overlies metallization 4. Via holes 8 which are to be opened in layer 7 are defined by ion etch mask 9. When ion etching is carried out in the usual manner, mask 9 protects layer 7, portions of which are removed at via holes 8. Ion etching of layer 7 proceeds as a result of the generation of a negative self-biased DC voltage at the top surface of layer 7 which accelerates the ions. Etching action stops completely at areas where layer 7 is removed completely as at via holes 8, since at these areas underlying metallization 4 is exposed and no DC bias voltage c...