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Correction of Initial Nonlinearity in a Ramp Type ADC

IP.com Disclosure Number: IPCOM000090101D
Original Publication Date: 1969-Feb-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Cochrane, FP: AUTHOR

Abstract

Ramp type analog-to-digital converters ADC for converting an analog voltage to a digital number operate by comparing a ramp voltage to an input voltage. A proportional time interval from the start of the ramp to the time the ramp and input voltages are equal. The number of precision clock pulses counted during this time interval is proportional to the amplitude of the input signal. However, nonlinearity in the ramp voltage at low signal levels causes the conversion to exhibit a nonlinear transfer function. This circuit overcomes this nonlinearity by offsetting the low level portion of the ramp and inhibiting the input to the counter during this interval.

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Correction of Initial Nonlinearity in a Ramp Type ADC

Ramp type analog-to-digital converters ADC for converting an analog voltage to a digital number operate by comparing a ramp voltage to an input voltage. A proportional time interval from the start of the ramp to the time the ramp and input voltages are equal. The number of precision clock pulses counted during this time interval is proportional to the amplitude of the input signal. However, nonlinearity in the ramp voltage at low signal levels causes the conversion to exhibit a nonlinear transfer function. This circuit overcomes this nonlinearity by offsetting the low level portion of the ramp and inhibiting the input to the counter during this interval.

The ramp generator consists of capacitor 11, constant current source 13, zero offset supply 15, and transistor 17. In the reset condition, transistor 17 is saturated and the voltage at terminal 19 equals the supply 15 voltage. When a conversion is to be made, the signal from start circuit 21 drives transistor 17 out of saturation, starting the ramp by charging capacitor 11 and initiates a time delay in zero offset delay circuit 33. The input voltage from terminal 22 is applied to one leg of voltage comparator 23, while the ramp signal from terminal 19 is applied to the other. Circuit 21 thus directs the current from source 13 into capacitor 11 such that the voltage at terminal 19 is a linear function of time v=It/c. At the same time the ramp is started, the st...