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Controlled Retry on Storage Errors

IP.com Disclosure Number: IPCOM000090120D
Original Publication Date: 1969-Feb-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 48K

Publishing Venue

IBM

Related People

Creamer, MK: AUTHOR [+2]

Abstract

The arrangement controls the retry of readout in a data processing system employing more than one read-only storage. The system comprises master oscillator 3, and clock controls such as 5 and 7, one associated with each of the read-only storages in the system. The clock controls are constructed and arranged so that the supply from them of clocking pulses to the associated read-only storage can be inhibited by the supply to the clock control unit of a blocking signal from the other storage or storages in the system. Read-only storage 9 is governed by address register 11 and supplies outputs to output register 13, from which the controls are read out to system control through an And 15. This is governed by execute clock pulses provided from the output of And 17, which has one input supplied to it from clock control 5.

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Controlled Retry on Storage Errors

The arrangement controls the retry of readout in a data processing system employing more than one read-only storage. The system comprises master oscillator 3, and clock controls such as 5 and 7, one associated with each of the read-only storages in the system. The clock controls are constructed and arranged so that the supply from them of clocking pulses to the associated read- only storage can be inhibited by the supply to the clock control unit of a blocking signal from the other storage or storages in the system. Read-only storage 9 is governed by address register 11 and supplies outputs to output register 13, from which the controls are read out to system control through an And 15. This is governed by execute clock pulses provided from the output of And 17, which has one input supplied to it from clock control 5.

Storage 9 is provided with noise detector 19. Register 13 has connected to it parity error-detection circuit 21. The outputs of detector 19 and circuit 21 are supplied to the inputs of Or 23. Thus, in the event of either noise during readout of the storage or detection of a parity error, a retry status latch 25 is turned on to provide an output signal on a line 27. Such signal initiates a predetermined number of retries of readout. Line 27 also connects to clock control 7, which controls the other storage, so that when latch 25 is set on, the clock drive for the other storage is inhibited. Also, the output of Or 23...