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Fail Safe Register

IP.com Disclosure Number: IPCOM000090127D
Original Publication Date: 1969-Feb-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 36K

Publishing Venue

IBM

Related People

Jessep, DC: AUTHOR

Abstract

Fail-safe logic circuits, of the type described in "Basic Properties and Construction Method for a Fail-Safe Logical System," IEEE-TEC. Vol. EC-16 No. 3 June 1967 pp. 282-289, can be extended into use with sequential logic circuitry. One type of fail-safe logic element described in the article is a simple flip-flop. These flip-flops are specified in the drawing by a 0 to have both outputs fail to the logic 0 state whenever a failure in the flip-flop occurs. Alternatively, the flip-flops can have both outputs fail to the logic 1 state whenever a failure occurs.

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Fail Safe Register

Fail-safe logic circuits, of the type described in "Basic

Properties and Construction Method for a Fail-Safe Logical System," IEEE-TEC. Vol. EC-16 No. 3 June 1967 pp. 282-289, can be extended into use with sequential logic circuitry. One type of fail-safe logic element described in the article is a simple flip-flop. These flip-flops are specified in the drawing by a 0 to have both outputs fail to the logic 0 state whenever a failure in the flip-flop occurs.

Alternatively, the flip-flops can have both outputs fail to the logic 1 state whenever a failure occurs.

The storage register in the drawing utilizes such flip-flops in which each bit storage position, or cell, is a fail-to-0 flip-flop. To insure the detection of the unfailing state of each cell, both outputs of the cell, the 1 and 0, are monitored by a Nor, also fail-safe device. Each Nor block is arranged to fail-to-1 so that its output fails to the logic 1 state whenever a failure occurs. The outputs off all Nor's are used as the inputs to a fail-safe, fail-to-1 Or. The output of this Or can be used for a failure indicator alarm.

When any flip-flop F-F of the register fails to the 00 state, the attached Nor switches state from the normal 0 to a 1. This changes the output of the Or from a 0 to a 1 and activates the alarm. Assume, instead, that the register F-F's function properly but that the output of one Nor fails to 1. Again the alarm is activated. Finally suppose that all F-F's and all...