Browse Prior Art Database

Delay Line Shifting Circuitry

IP.com Disclosure Number: IPCOM000090141D
Original Publication Date: 1969-Feb-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 31K

Publishing Venue

IBM

Related People

Igel, JJ: AUTHOR [+2]

Abstract

The circuitry causes the shift of a data character in a delay line circuit, including delay line 20 and shift register 21, by applying a timed input to A Reg Bypass or Recycle A Reg. The delay line circuit includes And's 22 and 23 and Or's 24 and 25. Data in the form of a series of memory words, each of which includes characters A...G, is gated into and is maintained in circulation in the circuit. And 26 is connected to Or 24 and to the output side of A Reg 21. Inverter 127 is connected to And 22. Recycle A Reg is connected to And 26 and 127. And 28 is connected to the output end of delay 20 and also to Or 25. Inverter 129 is connected to And 23. A Reg Bypass is connected to And 28 and 129.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 95% of the total text.

Page 1 of 2

Delay Line Shifting Circuitry

The circuitry causes the shift of a data character in a delay line circuit, including delay line 20 and shift register 21, by applying a timed input to A Reg Bypass or Recycle A Reg. The delay line circuit includes And's 22 and 23 and Or's 24 and 25. Data in the form of a series of memory words, each of which includes characters A...G, is gated into and is maintained in circulation in the circuit. And 26 is connected to Or 24 and to the output side of A Reg 21. Inverter 127 is connected to And 22. Recycle A Reg is connected to And 26 and 127. And 28 is connected to the output end of delay 20 and also to Or 25. Inverter 129 is connected to And 23.

A Reg Bypass is connected to And 28 and 129. A character in any memory word can be shifted to the preceding position by applying a signal to A Reg Bypass synchronized with the preceding character which erases the old preceding character and gates the output of delay 20 directly to its input through And 28 and Or 25. Character F can thus be shifted to E position by applying a signal synchronized with character E: A character can be shifted to the following position by applying a signal to Recycle A Reg synchronized with the character which inhibits the following character from entering A Reg 21 and gates the output of A Reg 21 directly to its input through And's 26 and 24. Character F, for example, can thus be shifted to the G position by applying a signal synchronized with the F character.

1...