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Parallel Reset Shift Register with Exclusive OR Latches

IP.com Disclosure Number: IPCOM000090144D
Original Publication Date: 1969-Feb-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 51K

Publishing Venue

IBM

Related People

Kennedy, JJ: AUTHOR [+3]

Abstract

Dual-rank shift register 10, drawing A, has Exclusive-Or bit latches B1...Bn and Exclusive-Or store latches S1...Sn. Two-phase clock lines 16 and 17 couple advance pulses to control input 13 of B1...Bn and S1...Sn respectively. Data line 18 is connected to data input 14 of S1. Data input 14 of each subsequent latch is fed by output 15 of the latch immediately preceding it. An X-Or latch retains the state of its previous output until a pulse appears at its control input. When such a control pulse appears, the latch output assumes a state representative of the complement of the data input. Hence, a pulse 19, drawing B, on line 16 passes the complements of S1...Sn to associated B1...Bn. A pulse 20 on line 17 moves the complement of B1...Bn one place to the right in S1...Sn.

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Parallel Reset Shift Register with Exclusive OR Latches

Dual-rank shift register 10, drawing A, has Exclusive-Or bit latches B1...Bn and Exclusive-Or store latches S1...Sn. Two-phase clock lines 16 and 17 couple advance pulses to control input 13 of B1...Bn and S1...Sn respectively. Data line 18 is connected to data input 14 of S1. Data input 14 of each subsequent latch is fed by output 15 of the latch immediately preceding it. An X-Or latch retains the state of its previous output until a pulse appears at its control input. When such a control pulse appears, the latch output assumes a state representative of the complement of the data input. Hence, a pulse 19, drawing B, on line 16 passes the complements of S1...Sn to associated B1...Bn. A pulse 20 on line 17 moves the complement of B1...Bn one place to the right in S1...Sn. The output of register 10 then appears on parallel bit lines 21.

Some shift registers are reset by forcing a data input line to a logical 0 until a succession of clock pulses clears all stages. Register reset time is then proportional to the register length. Alternatively, reset can be achieved in a single cycle time by forcing all data input to a known value simultaneously. This requires substantial additional circuitry. Register 10 achieves a reset function in a single cycle time with a minimum of extra logic by providing reset inputs 22 on S1...Sn. Reset line 23 is coupled to all inputs 22 through gate 24. Line 23 is also tied into line 16 through Or 25. An asynchronous reset pulse 26...