Browse Prior Art Database

Serial Parallel Buffer

IP.com Disclosure Number: IPCOM000090160D
Original Publication Date: 1969-Feb-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 53K

Publishing Venue

IBM

Related People

Davis, DE: AUTHOR [+3]

Abstract

This buffer operates in any combination of serial-in, serial-out, parallel-in, parallel-out data modes.

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Serial Parallel Buffer

This buffer operates in any combination of serial-in, serial-out, parallel-in, parallel-out data modes.

For a serial write operation, the first data bit appearing on the serial I/O line during slot T1 is written into bit 5. To accomplish this, all bit gating inputs, B1...B5, the word line input WL, and sense amplifier gate G1 are conditioned on. Under these gating conditions, the combination of a bit driver and sense amplifier, for the first four bits, can be considered as a noninverting amplifier. The input data on the I/O line therefore propagates through to the input of bit driver 5 and is written into array position 5. The fact that the data is also written into the first four bits is incidental. Bit gating input B5 is then turned off and the next data bit appearing during slot time T2 is written into array position 4. The first data bit remains stored in position 5 since B5 is off. During slot T3, B4 and B5 are turned off and the input data are stored in position 3. This sequence is continued until all bits are written into the array. The storage location for this 5- bit character is dependent on whatever word WL was selected by X and Y inputs during the five slot times.

To read this same information out serially, the operation is somewhat similar. Data bit 1, stored in position 5, is read by selecting the proper X and Y inputs and turning on G2. Bit 2 is read by turning on G2, G1, B5 and WL. The output of sense amplifier 4 then appear...