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IP.com Disclosure Number: IPCOM000090184D
Original Publication Date: 1969-Feb-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Axford, JG: AUTHOR [+2]

Abstract

A storage array has a series of matrices P of storage cells, each provided with rows of bit-sense conductors B and columns of word conductors W. Each conductor B of each matrix P is connected in series with a bit conductor from each of a number of other matrices P so as to form a bit-sense line which links a number of storage locations in a number of matrices. Each conductor W of each matrix P is connected in series with a word conductor from each of a number of other matrices P so as to form a word conductor which links a number of storage locations in a number of matrices. The bit storage locations which share a common bit-sense line are read by sending a pulse along a line W which also links those locations and which causes a serial train of output pulses to appear on the line B.

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A storage array has a series of matrices P of storage cells, each provided with rows of bit-sense conductors B and columns of word conductors W. Each conductor B of each matrix P is connected in series with a bit conductor from each of a number of other matrices P so as to form a bit-sense line which links a number of storage locations in a number of matrices. Each conductor W of each matrix P is connected in series with a word conductor from each of a number of other matrices P so as to form a word conductor which links a number of storage locations in a number of matrices. The bit storage locations which share a common bit-sense line are read by sending a pulse along a line W which also links those locations and which causes a serial train of output pulses to appear on the line B.

The pulses in the train are separated from one another by reason of the spacing of the storage locations along line 8 and along line W.

The interconnections of conductors B and conductors W to form the bit-sense lines and word lines is such that the electrical line length between successive intersections of line W with line 8 is constant. As a result, variation in the spacing between successive output pulses appearing on a line B is avoided.

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