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Dynamic MOSFET Logic Circuit

IP.com Disclosure Number: IPCOM000090188D
Original Publication Date: 1969-Mar-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 28K

Publishing Venue

IBM

Related People

Montren, JJ: AUTHOR

Abstract

FET's T1 and T3 are activated with the application of timing pulse phi 1. The gate capacitance of FET T5' and the node N1 capacitance are charged to -V through T1. At the same time, the node N2 capacitance is primed in the positive or negative direction depending upon the state of FET's T4 and T5 by FET T3. The priming of the node N2 capacitance improves performance and eliminates the possibility of charge splitting between node N1 and N2. When timing pulse phi 2 is applied to the gate of FET T2, the latter is activated permitting the charge on node N1 to remain or be discharged as a function of the condition of T4 and T5. The process is repeated by timing pulses phi 3 and phi 4 with the data output being available at the completion of pulse phi 4.

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Dynamic MOSFET Logic Circuit

FET's T1 and T3 are activated with the application of timing pulse phi 1. The gate capacitance of FET T5' and the node N1 capacitance are charged to -V through T1. At the same time, the node N2 capacitance is primed in the positive or negative direction depending upon the state of FET's T4 and T5 by FET T3. The priming of the node N2 capacitance improves performance and eliminates the possibility of charge splitting between node N1 and N2. When timing pulse phi 2 is applied to the gate of FET T2, the latter is activated permitting the charge on node N1 to remain or be discharged as a function of the condition of T4 and T5. The process is repeated by timing pulses phi 3 and phi 4 with the data output being available at the completion of pulse phi 4. The use of FET's T3 and T3' and the DC busses permits a reduction in the normal four-phase clock load, thus improving performance, reducing power dissipation and current drive.

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