Browse Prior Art Database

Use of a Buried Layer for Low Power FET Cells

IP.com Disclosure Number: IPCOM000090207D
Original Publication Date: 1969-Mar-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 26K

Publishing Venue

IBM

Related People

Gladu, RG: AUTHOR

Abstract

Backbiased diode 1, drawing B, can be formed under a FET 2 and used as a load for the FET. N+ diffusion 10, drawing A, is placed in the backside of a P substrate 12 having a FET formed on its top surface. N+ diffusion 10 is directly under either the source 14 or the drain 16 diffusion for the FET. Thus when N+ region 10 is connected to positive terminal +V, it forms a backbiased diode load 1 connected in series with the FET 2 positioned over it on substrate 12.

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Use of a Buried Layer for Low Power FET Cells

Backbiased diode 1, drawing B, can be formed under a FET 2 and used as a load for the FET. N+ diffusion 10, drawing A, is placed in the backside of a P substrate 12 having a FET formed on its top surface. N+ diffusion 10 is directly under either the source 14 or the drain 16 diffusion for the FET. Thus when N+ region 10 is connected to positive terminal +V, it forms a backbiased diode load 1 connected in series with the FET 2 positioned over it on substrate 12.

This diode-FET combination can be used in a storage cell of a memory. As shown, the FET's 2 are crosscoupled to form a bistable circuit and are connected to the addressing lines of the memory by additional FET's 3. While the cell is not being addressed, FET's 3 are biased off so that the potentials at the nodes 4 are maintained by the leakage currents flowing through the backbiased diodes 1. For proper operation of the circuit there is a requirement that the leakage currents of the reverse biased load diodes 1 be greater than the leakage currents from the drain diffusions of the FET's 2 and 3 to substrate 12. This requirement can be satisfied by making the junction area of a load diode 1 sufficiently large and by using appropriate doping levels.

The structure and circuit shown can be constructed with a minimum amount of wafer surface area because no space is used to fabricate diodes 1.

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