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MOSFET Substrate Bias Voltage Generator

IP.com Disclosure Number: IPCOM000090208D
Original Publication Date: 1969-Mar-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 31K

Publishing Venue

IBM

Related People

Frantz, H: AUTHOR [+2]

Abstract

This circuit supplies a negative potential to bias FET substrates without a separate negative voltage supply. A positive waveform potential 10, drawing A, is developed from a positive source for the FET's on the substrate. This potential 10 is applied at the input terminals 12 and 14 of the circuit in drawing B. When the potential 10 reaches its peak, capacitor C1 is charged to that peak voltage minus the threshold voltage of FET 16 which conducts while the potential is increasing. However as the potential starts dropping FET 12 stops conducting allowing the cathode of diode D1 to swing negative as the potential at terminal 12 decreases. This charges substrate 20 to a negative potential through the ground to substrate capacitance C2 and the diode.

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MOSFET Substrate Bias Voltage Generator

This circuit supplies a negative potential to bias FET substrates without a separate negative voltage supply. A positive waveform potential 10, drawing A, is developed from a positive source for the FET's on the substrate. This potential 10 is applied at the input terminals 12 and 14 of the circuit in drawing B. When the potential 10 reaches its peak, capacitor C1 is charged to that peak voltage minus the threshold voltage of FET 16 which conducts while the potential is increasing. However as the potential starts dropping FET 12 stops conducting allowing the cathode of diode D1 to swing negative as the potential at terminal 12 decreases. This charges substrate 20 to a negative potential through the ground to substrate capacitance C2 and the diode.

The circuit is fabricated on the monolithic chip as shown at C and D. C1 must be very much larger than capacitance C2.

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