Browse Prior Art Database

Interconnection Control Networks

IP.com Disclosure Number: IPCOM000090216D
Original Publication Date: 1969-Mar-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 3 page(s) / 43K

Publishing Venue

IBM

Related People

Schneider, PR: AUTHOR

Abstract

Drawing A shows a redundant switching arrangement applicable to ultra-reliable available computing systems. It is used to perform reconfiguration in a standby redundancy system, switching between various devices in a multiprocessing system, and many other related tasks. Control section 10 issues sequences of encoded addresses or commands to bus 14. Master switches 12 respond to certain of these address commands in order to change the interconnection structure or reconfigure the system. Devices synthesize master switches 12 so they become ultrareliable. The switching arrangement is particularly suited to the nonlogic portions of a computer system such as power and clocking distribution networks.

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Interconnection Control Networks

Drawing A shows a redundant switching arrangement applicable to ultra- reliable available computing systems. It is used to perform reconfiguration in a standby redundancy system, switching between various devices in a multiprocessing system, and many other related tasks. Control section 10 issues sequences of encoded addresses or commands to bus 14. Master switches 12 respond to certain of these address commands in order to change the interconnection structure or reconfigure the system. Devices synthesize master switches 12 so they become ultrareliable. The switching arrangement is particularly suited to the nonlogic portions of a computer system such as power and clocking distribution networks.

Drawing C shows an information Line Switch LS actuated by encoded addresses coming off a central control bus. These addresses can be interpreted as commands to LS. As the address leaves the bus, it enters both Address Correctors AC where the error correction encoding is used to generate an address which has been corrected for errors occurring in the bus. One AC drives Reset Address Detector RAD. The other AC drives Set Address Detector SAD At some saving in circuitry, but sacrifice in reliability, RAD and SAD can share a common AC. RAD is used to detect the existence on the bus of the address or command used to reset Control Latch CL. SAD detects the address or command used to set the CL. When the CL is set, Information Gate IG is closed and information can flow through it. When the CL is reset, the IG is open and no information passes through the gate. Thus it requires a positive action, i.e., placing the correct address or command on the bus, to change the status of the IG.

For ultrareliable switching a typical Master Switch MS, shown in B, co...