Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Parity Check Circuit for Unequal Byte Size Transfers

IP.com Disclosure Number: IPCOM000090226D
Original Publication Date: 1969-Mar-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 24K

Publishing Venue

IBM

Related People

Macak, RW: AUTHOR [+2]

Abstract

When transferring data between two systems which do not have the same number of bits per byte but each of which carries one parity bit per byte, the transfer operation is parity checked. The writing system transmits its data bits to a buffer BFR. The overall parity of the data of the writing system is determined by using binary trigger T1 to detect the parity of the several byte parity bits. This parity bit is transmitted to BFR and represents the parity of all of the data stored within BFR. As the reading system takes data from BFR, a second parity bit is formed and stored in register B. This bit is formed by trigger T2 from the individual bits of the data transferred to the reading system. After BFR is emptied, the parity A and B bits are compared. If they are equal, a parity error has not occurred.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 2

Parity Check Circuit for Unequal Byte Size Transfers

When transferring data between two systems which do not have the same number of bits per byte but each of which carries one parity bit per byte, the transfer operation is parity checked. The writing system transmits its data bits to a buffer BFR. The overall parity of the data of the writing system is determined by using binary trigger T1 to detect the parity of the several byte parity bits. This parity bit is transmitted to BFR and represents the parity of all of the data stored within BFR. As the reading system takes data from BFR, a second parity bit is formed and stored in register B. This bit is formed by trigger T2 from the individual bits of the data transferred to the reading system. After BFR is emptied, the parity A and B bits are compared. If they are equal, a parity error has not occurred. If they are unequal, an error signal is generated at the output of Inverter I.

1

Page 2 of 2

2

[This page contains 2 pictures or other non-text objects]